1 note: this is a summary document. a complete document is available under nda. for more information, please contact your local atmel sales office. features ? full tcg/tcpa v1.1b compatibility single chip turnkey solution hardware asymmetric crypto engine 2048 rsa sign in 500 ms using crt avr 8-bit risc microprocessor internal eeprom storage for 10+ rsa keys 33 mhz lpc (low pin count) bus for easy pc interface 100 khz system management bus (smbus) two-wire interface secure hardware and firmware design and chip layout true random number generator (rng) secure real-time clock option 3.3v 10% supply voltage 28-lead tssop package or 40-lead mlf package 0?70 c temperature range description the at97sc3201 is a fully integrated security module designed to be integrated into personal computers and other embedded systems. it implements version 1.1b of the trusted computing platform alliance (tcpa) specification for trusted platform modules (tpm). this specification has been adopted by the trusted computing group (tcg). the tpm includes a crypto accelerator capable of computing a 2048-bit rsa signature in 500 ms and a 1024-bit rsa signature in 100 ms, both using crt. communication to and from the tpm can occur through one of two interface protocols: either a 33-mhz lpc interface or a 100-khz smbus two-wire interface. figure 1. at97sc3201 block diagram the chip includes a full hardware random number generator that is used for the tcg protocol and is also available to the system for any random numbers it may need during normal operation. 33 mhz lpc interface avr 8/16 bit cpu physical security circuitry smbclk/ioa smbus interface or gpio rtc v bb 32.768 khz rng timer rom program eeprom program eeprom data crypto engine sram ioc smbdat/iob trusted platform module at97sc3201 summary rev. 2015ds-tpm?7/04
2 at97sc3201 2015ds-tpm?7/04 a real-time clock function is available using an external battery and crystal. the chip provides tamper detection if the battery or crystal are removed or tampered with, and the current time value can be signed by the appropriate internal keys to verify its accuracy. (contact atmel for current status of this option.) the battery detector can be used without the crystal for lower cost. in this mode, the tpm can indicate to the system if it has been removed from the pc in any way and can also take actions internally. the chip uses a dynamic internal memory management scheme to store from 10 to 20 keys. other than the standard tcg commands (tpm_evictkey, tpm_loadkey), no system inter- vention is required to manage this internal key cache. the tpm is offered to oem manufacturers as a turnkey solution, including the firmware inte- grated on the chip. in addition, atmel provides the necessary driver software for integration into certain operating systems, along with bios drivers. a tcg software stack (tss), also supplied by atmel and available under license, provides communication support to any appli- cation using mscapi or pkcs #11 cryptographic apis. (contact atmel for a complete list of operating systems supported.) full documentation for tcg primitives can be found on the tcg web site, www.trustedcomputinggroup.org . this specification includes only mechanical and electrical information.
3 at97sc3201 2015ds-tpm?7/04 absolute maximum ratings * v cc = 3.0 to 3.6v; temperature = 0 to 70 c note: these parameters guaranteed but not tested. operating temperature..............................0c to +70c storage temperature (without bias)...........0c to + 70c voltage on i/o pins.............................. ? 0.1 to v cc +0.3v voltage on vcc with respect to ground.................6.0v maximum esd voltage..........................................2000v *notice: stresses beyond those listed under ? absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification may cause temporary or permanent failure. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 1 . dc parameters* symbol parameter min nom max units notes v cc supply voltage 3.0 3.3 3.6 v i cc operating current at fclk = 33 mhz 25 50 ma i st static current 5 10 ma v cc = 3.6v; fxtal = 0 hz, active inputs i sl sleep current, chip idle 40 100 a v cc = 3.6v; fxtal = 0 hz i bb battery current 2 4 a v cc = 0v; fxtal = 0 hz. i lio input leakage 0.1 3 a vin = v cc or gnd v ih input high threshold 0.5 * v cc v cc + 0.5 v v il input low threshold ? 0.5 0.3 * v cc v v oh output high voltage 0.9 * v cc 0.98 * v cc v at i out = ? 500 ua v ol output low voltage 0.1 * v cc vat i out = 1.5ma i olcr output low current, clkrun# 7 ma at v out = .615 * v cc c i input pin capacitance 6 pf note 1
4 at97sc3201 2015ds-tpm?7/04 * cl = 10pf. v cc = 3.0 to 3.7v; temperature = 0 to 70 c note: 1. all parameters measured with respect to signal crossing vtest = 0.4 * v cc unless otherwise noted. 2. these parameters guaranteed but not tested. 3. the minimum parameter must never be violated under any circumstances unless ireset# is asserted. if proper clkrun# signaling is observed, the maximum specification can be violated. table 2 . ac parameters* symbol parameter min nom max units notes t va l clk to signal valid delay ? lad0-3 2 5 11 ns measured at vtrise = 0.285 * v cc and vtfal = 0.615 * v cc . measured from clk at vtest = 0.4 * v cc ; load = 200 ? t on float to active delay 2 4 ns t off active to float delay 28 ns t su input setup time to clk 7 2 ns t h input hold time from clk 0 ? 500 ns t rst reset active time after power stable 1 ms note 2 t rst-clk reset active after clk stable 100 m note 2 t rst-off reset active to output float delay 40 ns note 2 t clkin clk period 29.5 30 31 ns note 3 t clklo clk low duration 13.4 18 ns note 1, note 3 t clkhi clk high duration 13.4 18 ns note 1, note 3 table 3 . ordering information ordering code package operation range at97sc3201-01ac 28a3 commercial (0 to 70 c) at97sc3201-x1ac 28a3 lead-free commercial (0 to 70 c) AT97SC3201-01MC 40ml1 commercial (0 to 70 c) at97sc3201-x1mc 40ml1 lead-free commercial (0 to 70 c)
5 at97sc3201 2015ds-tpm?7/04 package drawing 28a3 ? tssop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 1/8/02 common dimensions (unit of measure = mm) symbol min nom max note d 9.60 9.70 9.80 2, 5 e 8.10 bsc e1 6.00 6.10 6.20 3, 5 a ?? 1.20 a2 0.80 1.00 1.05 b 0.19 ? 0.30 4 e 0.65 bsc l 0.45 0.60 0.75 l1 1.00 ref 28a3 , 28-lead, 6.1 x 9.7 mm body, 0.65 pitch, thin shrink small outline package (tssop) notes: 1. this drawing is for general information only. please refer to jedec drawing mo-153, variation db for additional informa tion. 2. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. dimension e1 does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.25 mm (0.0 10 in) per side. 4. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. dambar cannot be located on the lower radius of the foot. minimum space between protrusion and adjacent lead is 0.07 mm. 5. dimension d and e1 to be determined at datum plane h. 28a3 a l1 a l d a2 e e1 e b top view side view end view
6 at97sc3201 2015ds-tpm?7/04 40ml1 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. a1 a3 a a2 0 side view 40ml1 , 40-lead 6.0 x 6.0 mm body, 0.50 mm pitch, molded quad flat no lead package (mlf2) a 40ml1 3/9/04 notes: 1. this drawing is for general information only. refer to jedec drawing mo-220, variation wjjd-2, for proper dimensions, tolerances, datums, etc. 2. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. common dimensions (unit of measure = mm) symbol min nom max note d 6.00 bsc e 6.00 bsc d2 3.95 4.10 4.25 e2 3.95 4.10 4.25 a - 0.85 0.90 a1 0.0 0.01 0.05 a2 - 0.65 0.70 a3 0.20 ref l 0.30 0.40 0.50 e 0.50 bsc b 0.18 0.23 0.30 2 d e top view n 2 3 1 pin 1 indicator l pin1 id b n d2 3 2 1 e bottom view e2
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